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ADV7401
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
P32
1
75
AIN12
P31
INT
CS/HS
DGND
DVDDIO
P15
P14
P13
P12
DGND
DVDD
P29
P28
SFL/SYNC_OUT
SCLK2
DGND
DVDDIO
SDA2
P11
P10
P9
P8
P27
P7
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIN 1
ADV7401
LQFP
TOP VIEW
(Not to Scale)
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
AIN5
AIN11
AIN4
AIN10
TEST0
CAPC2
CAPC1
BIAS
AGND
CML
REFOUT
AVDD
CAPY2
CAPY1
AGND
TEST1
AIN3
AIN9
AIN2
AIN8
AIN1
AIN7
SOG
FB
Figure 2. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
5, 11, 17, 40, 89
49, 50, 60, 66
6, 18
12, 39, 90
63
47, 48
51
Mnemonic
DGND
AGND
DVDDIO
DVDD
AVDD
PVDD
FB
Type
G
G
P
P
P
P
I
Function
Digital Ground.
Analog Ground.
Digital I/O Supply Voltage (3.3 V).
Digital Core Supply Voltage (1.8 V).
Analog Supply Voltage (3.3 V).
PLL Supply Voltage (1.8 V).
Fast Switch Overlay Input. This pin switches between CVBS and RGB
analog signals.
54, 56, 58, 72, 74, 76, 53, 55,
AIN1 to AIN12
I
Analog Video Input Channels.
57, 71, 73, 75
42, 41, 28, 27, 26, 25, 23, 22,
P2 to P9, P12 to P19
O
Video Pixel Output Port.
10, 9, 8, 7, 94, 93, 92, 91
33, 32, 31, 30, 29, 24, 14, 13
44, 43, 21, 20, 45, 34, 2, 1,
100, 97, 96, 95, 88, 87, 84, 83
3
P22 to P29
P0 to P1, P10 to P11,
P20 to P21, P31 to P40
INT
I/O
I
O
Video Input/Output Port
Video Pixel Input Port.
Interrupt. This pin can be active low or active high. When SDP/CP status
bits change this pin triggers. The set of events that triggers an interrupt
is under user control.
Rev. B | Page 10 of 20
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